
use crate::metadata::ir::*;
pub(crate) static REGISTERS: IR = IR {
    blocks: &[Block {
        name: "Rcc",
        extends: None,
        description: Some("Reset and clock control"),
        items: &[
            BlockItem {
                name: "cr",
                description: Some("Clock control register"),
                array: None,
                byte_offset: 0x0,
                inner: BlockItemInner::Register(Register {
                    access: Access::ReadWrite,
                    bit_size: 32,
                    fieldset: Some("Cr"),
                }),
            },
            BlockItem {
                name: "icscr",
                description: Some("Internal clock sources calibration register"),
                array: None,
                byte_offset: 0x4,
                inner: BlockItemInner::Register(Register {
                    access: Access::ReadWrite,
                    bit_size: 32,
                    fieldset: Some("Icscr"),
                }),
            },
            BlockItem {
                name: "cfgr",
                description: Some("Clock configuration register"),
                array: None,
                byte_offset: 0x8,
                inner: BlockItemInner::Register(Register {
                    access: Access::ReadWrite,
                    bit_size: 32,
                    fieldset: Some("Cfgr"),
                }),
            },
            BlockItem {
                name: "pllcfgr",
                description: Some("PLL configuration register"),
                array: None,
                byte_offset: 0xc,
                inner: BlockItemInner::Register(Register {
                    access: Access::ReadWrite,
                    bit_size: 32,
                    fieldset: Some("Pllcfgr"),
                }),
            },
            BlockItem {
                name: "crrcr",
                description: Some("RCC clock recovery RC register"),
                array: None,
                byte_offset: 0x14,
                inner: BlockItemInner::Register(Register {
                    access: Access::Read,
                    bit_size: 32,
                    fieldset: Some("Crrcr"),
                }),
            },
            BlockItem {
                name: "cier",
                description: Some("Clock interrupt enable register"),
                array: None,
                byte_offset: 0x18,
                inner: BlockItemInner::Register(Register {
                    access: Access::ReadWrite,
                    bit_size: 32,
                    fieldset: Some("Cier"),
                }),
            },
            BlockItem {
                name: "cifr",
                description: Some("Clock interrupt flag register"),
                array: None,
                byte_offset: 0x1c,
                inner: BlockItemInner::Register(Register {
                    access: Access::Read,
                    bit_size: 32,
                    fieldset: Some("Cifr"),
                }),
            },
            BlockItem {
                name: "cicr",
                description: Some("Clock interrupt clear register"),
                array: None,
                byte_offset: 0x20,
                inner: BlockItemInner::Register(Register {
                    access: Access::Write,
                    bit_size: 32,
                    fieldset: Some("Cicr"),
                }),
            },
            BlockItem {
                name: "gpiorstr",
                description: Some("GPIO reset register"),
                array: None,
                byte_offset: 0x24,
                inner: BlockItemInner::Register(Register {
                    access: Access::ReadWrite,
                    bit_size: 32,
                    fieldset: Some("Gpiorstr"),
                }),
            },
            BlockItem {
                name: "ahbrstr",
                description: Some("AHB peripheral reset register"),
                array: None,
                byte_offset: 0x28,
                inner: BlockItemInner::Register(Register {
                    access: Access::ReadWrite,
                    bit_size: 32,
                    fieldset: Some("Ahbrstr"),
                }),
            },
            BlockItem {
                name: "apbrstr1",
                description: Some("APB peripheral reset register 1"),
                array: None,
                byte_offset: 0x2c,
                inner: BlockItemInner::Register(Register {
                    access: Access::ReadWrite,
                    bit_size: 32,
                    fieldset: Some("Apbrstr1"),
                }),
            },
            BlockItem {
                name: "apbrstr2",
                description: Some("APB peripheral reset register 2"),
                array: None,
                byte_offset: 0x30,
                inner: BlockItemInner::Register(Register {
                    access: Access::ReadWrite,
                    bit_size: 32,
                    fieldset: Some("Apbrstr2"),
                }),
            },
            BlockItem {
                name: "gpioenr",
                description: Some("GPIO clock enable register"),
                array: None,
                byte_offset: 0x34,
                inner: BlockItemInner::Register(Register {
                    access: Access::ReadWrite,
                    bit_size: 32,
                    fieldset: Some("Gpioenr"),
                }),
            },
            BlockItem {
                name: "ahbenr",
                description: Some("AHB peripheral clock enable register"),
                array: None,
                byte_offset: 0x38,
                inner: BlockItemInner::Register(Register {
                    access: Access::ReadWrite,
                    bit_size: 32,
                    fieldset: Some("Ahbenr"),
                }),
            },
            BlockItem {
                name: "apbenr1",
                description: Some("APB peripheral clock enable register 1"),
                array: None,
                byte_offset: 0x3c,
                inner: BlockItemInner::Register(Register {
                    access: Access::ReadWrite,
                    bit_size: 32,
                    fieldset: Some("Apbenr1"),
                }),
            },
            BlockItem {
                name: "apbenr2",
                description: Some("APB peripheral clock enable register 2"),
                array: None,
                byte_offset: 0x40,
                inner: BlockItemInner::Register(Register {
                    access: Access::ReadWrite,
                    bit_size: 32,
                    fieldset: Some("Apbenr2"),
                }),
            },
            BlockItem {
                name: "gpiosmenr",
                description: Some("GPIO in Sleep mode clock enable register"),
                array: None,
                byte_offset: 0x44,
                inner: BlockItemInner::Register(Register {
                    access: Access::ReadWrite,
                    bit_size: 32,
                    fieldset: Some("Gpiosmenr"),
                }),
            },
            BlockItem {
                name: "ahbsmenr",
                description: Some("AHB peripheral clock enable in Sleep mode register"),
                array: None,
                byte_offset: 0x48,
                inner: BlockItemInner::Register(Register {
                    access: Access::ReadWrite,
                    bit_size: 32,
                    fieldset: Some("Ahbsmenr"),
                }),
            },
            BlockItem {
                name: "apbsmenr1",
                description: Some("APB peripheral clock enable in Sleep mode register 1"),
                array: None,
                byte_offset: 0x4c,
                inner: BlockItemInner::Register(Register {
                    access: Access::ReadWrite,
                    bit_size: 32,
                    fieldset: Some("Apbsmenr1"),
                }),
            },
            BlockItem {
                name: "apbsmenr2",
                description: Some("APB peripheral clock enable in Sleep mode register 2"),
                array: None,
                byte_offset: 0x50,
                inner: BlockItemInner::Register(Register {
                    access: Access::ReadWrite,
                    bit_size: 32,
                    fieldset: Some("Apbsmenr2"),
                }),
            },
            BlockItem {
                name: "ccipr",
                description: Some("Peripherals independent clock configuration register"),
                array: None,
                byte_offset: 0x54,
                inner: BlockItemInner::Register(Register {
                    access: Access::ReadWrite,
                    bit_size: 32,
                    fieldset: Some("Ccipr"),
                }),
            },
            BlockItem {
                name: "ccipr2",
                description: Some("Peripherals independent clock configuration register 2"),
                array: None,
                byte_offset: 0x58,
                inner: BlockItemInner::Register(Register {
                    access: Access::ReadWrite,
                    bit_size: 32,
                    fieldset: Some("Ccipr2"),
                }),
            },
            BlockItem {
                name: "bdcr",
                description: Some("RTC domain control register"),
                array: None,
                byte_offset: 0x5c,
                inner: BlockItemInner::Register(Register {
                    access: Access::ReadWrite,
                    bit_size: 32,
                    fieldset: Some("Bdcr"),
                }),
            },
            BlockItem {
                name: "csr",
                description: Some("Control/status register"),
                array: None,
                byte_offset: 0x60,
                inner: BlockItemInner::Register(Register {
                    access: Access::ReadWrite,
                    bit_size: 32,
                    fieldset: Some("Csr"),
                }),
            },
        ],
    }],
    fieldsets: &[
        FieldSet {
            name: "Ahbenr",
            extends: None,
            description: Some("AHB peripheral clock enable register"),
            bit_size: 32,
            fields: &[
                Field {
                    name: "dma1en",
                    description: Some("DMA1 clock enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "dma2en",
                    description: Some("DMA2 clock enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 1 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "flashen",
                    description: Some("Flash memory interface clock enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 8 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "crcen",
                    description: Some("CRC clock enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 12 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "aesen",
                    description: Some("AES hardware accelerator"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 16 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "rngen",
                    description: Some("Random number generator clock enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 18 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
            ],
        },
        FieldSet {
            name: "Ahbrstr",
            extends: None,
            description: Some("AHB peripheral reset register"),
            bit_size: 32,
            fields: &[
                Field {
                    name: "dma1rst",
                    description: Some("DMA1 reset"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "dma2rst",
                    description: Some("DMA1 reset"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 1 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "flashrst",
                    description: Some("FLASH reset"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 8 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "crcrst",
                    description: Some("CRC reset"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 12 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "aesrst",
                    description: Some("AES hardware accelerator reset"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 16 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "rngrst",
                    description: Some("Random number generator reset"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 18 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
            ],
        },
        FieldSet {
            name: "Ahbsmenr",
            extends: None,
            description: Some("AHB peripheral clock enable in Sleep mode register"),
            bit_size: 32,
            fields: &[
                Field {
                    name: "dma1smen",
                    description: Some("DMA1 clock enable during Sleep mode"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "dma2smen",
                    description: Some("DMA2 clock enable during Sleep mode"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 1 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "flashsmen",
                    description: Some("Flash memory interface clock enable during Sleep mode"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 8 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "sramsmen",
                    description: Some("SRAM clock enable during Sleep mode"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 9 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "crcsmen",
                    description: Some("CRC clock enable during Sleep mode"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 12 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "aessmen",
                    description: Some("AES hardware accelerator clock enable during Sleep mode"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 16 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "rngsmen",
                    description: Some("Random number generator clock enable during Sleep mode"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 18 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
            ],
        },
        FieldSet {
            name: "Apbenr1",
            extends: None,
            description: Some("APB peripheral clock enable register 1"),
            bit_size: 32,
            fields: &[
                Field {
                    name: "tim2en",
                    description: Some("TIM2 timer clock enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "tim3en",
                    description: Some("TIM3 timer clock enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 1 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "tim4en",
                    description: Some("TIM4 timer clock enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 2 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "tim6en",
                    description: Some("TIM6 timer clock enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 4 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "tim7en",
                    description: Some("TIM7 timer clock enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 5 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "lpuart2en",
                    description: Some("LPUART2 clock enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 7 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "usart5en",
                    description: Some("USART5EN"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 8 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "usart6en",
                    description: Some("USART6EN"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 9 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "rtcapben",
                    description: Some("RTC APB clock enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 10 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "wwdgen",
                    description: Some("WWDG clock enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 11 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "fdcanen",
                    description: Some("USBEN"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 12 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "usben",
                    description: Some("USBEN"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 13 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "spi2en",
                    description: Some("SPI2 clock enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 14 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "spi3en",
                    description: Some("SPI3 clock enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 15 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "crsen",
                    description: Some("CRSEN"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 16 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "usart2en",
                    description: Some("USART2 clock enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 17 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "usart3en",
                    description: Some("USART3 clock enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 18 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "usart4en",
                    description: Some("USART4 clock enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 19 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "lpuart1en",
                    description: Some("LPUART1 clock enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 20 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "i2c1en",
                    description: Some("I2C1 clock enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 21 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "i2c2en",
                    description: Some("I2C2 clock enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 22 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "i2c3en",
                    description: Some("I2C3 clock enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 23 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "cecen",
                    description: Some("HDMI CEC clock enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 24 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "ucpd1en",
                    description: Some("UCPD1 clock enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 25 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "ucpd2en",
                    description: Some("UCPD2 clock enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 26 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "dbgen",
                    description: Some("Debug support clock enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 27 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "pwren",
                    description: Some("Power interface clock enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 28 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "dac1en",
                    description: Some("DAC1 interface clock enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 29 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "lptim2en",
                    description: Some("LPTIM2 clock enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 30 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "lptim1en",
                    description: Some("LPTIM1 clock enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 31 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
            ],
        },
        FieldSet {
            name: "Apbenr2",
            extends: None,
            description: Some("APB peripheral clock enable register 2"),
            bit_size: 32,
            fields: &[
                Field {
                    name: "syscfgen",
                    description: Some("SYSCFG, COMP and VREFBUF clock enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "tim1en",
                    description: Some("TIM1 timer clock enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 11 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "spi1en",
                    description: Some("SPI1 clock enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 12 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "usart1en",
                    description: Some("USART1 clock enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 14 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "tim14en",
                    description: Some("TIM14 timer clock enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 15 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "tim15en",
                    description: Some("TIM15 timer clock enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 16 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "tim16en",
                    description: Some("TIM16 timer clock enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 17 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "tim17en",
                    description: Some("TIM16 timer clock enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 18 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "adcen",
                    description: Some("ADC clock enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 20 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
            ],
        },
        FieldSet {
            name: "Apbrstr1",
            extends: None,
            description: Some("APB peripheral reset register 1"),
            bit_size: 32,
            fields: &[
                Field {
                    name: "tim2rst",
                    description: Some("TIM2 timer reset"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "tim3rst",
                    description: Some("TIM3 timer reset"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 1 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "tim4rst",
                    description: Some("TIM4 timer reset"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 2 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "tim6rst",
                    description: Some("TIM6 timer reset"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 4 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "tim7rst",
                    description: Some("TIM7 timer reset"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 5 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "lpuart2rst",
                    description: Some("LPUART2RST"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 7 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "usart5rst",
                    description: Some("USART5RST"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 8 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "usart6rst",
                    description: Some("USART6RST"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 9 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "fdcanrst",
                    description: Some("FDCANRST"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 12 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "usbrst",
                    description: Some("USBRST"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 13 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "spi2rst",
                    description: Some("SPI2 reset"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 14 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "spi3rst",
                    description: Some("SPI3 reset"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 15 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "crsrst",
                    description: Some("CRSRST"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 16 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "usart2rst",
                    description: Some("USART2 reset"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 17 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "usart3rst",
                    description: Some("USART3 reset"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 18 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "usart4rst",
                    description: Some("USART4 reset"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 19 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "lpuart1rst",
                    description: Some("LPUART1 reset"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 20 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "i2c1rst",
                    description: Some("I2C1 reset"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 21 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "i2c2rst",
                    description: Some("I2C2 reset"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 22 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "i2c3rst",
                    description: Some("I2C3RST reset"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 23 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "cecrst",
                    description: Some("HDMI CEC reset"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 24 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "ucpd1rst",
                    description: Some("UCPD1 reset"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 25 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "ucpd2rst",
                    description: Some("UCPD2 reset"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 26 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "dbgrst",
                    description: Some("Debug support reset"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 27 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "pwrrst",
                    description: Some("Power interface reset"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 28 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "dac1rst",
                    description: Some("DAC1 interface reset"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 29 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "lptim2rst",
                    description: Some("Low Power Timer 2 reset"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 30 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "lptim1rst",
                    description: Some("Low Power Timer 1 reset"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 31 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
            ],
        },
        FieldSet {
            name: "Apbrstr2",
            extends: None,
            description: Some("APB peripheral reset register 2"),
            bit_size: 32,
            fields: &[
                Field {
                    name: "syscfgrst",
                    description: Some("SYSCFG, COMP and VREFBUF reset"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "tim1rst",
                    description: Some("TIM1 timer reset"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 11 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "spi1rst",
                    description: Some("SPI1 reset"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 12 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "usart1rst",
                    description: Some("USART1 reset"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 14 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "tim14rst",
                    description: Some("TIM14 timer reset"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 15 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "tim15rst",
                    description: Some("TIM15 timer reset"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 16 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "tim16rst",
                    description: Some("TIM16 timer reset"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 17 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "tim17rst",
                    description: Some("TIM17 timer reset"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 18 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "adcrst",
                    description: Some("ADC reset"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 20 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
            ],
        },
        FieldSet {
            name: "Apbsmenr1",
            extends: None,
            description: Some("APB peripheral clock enable in Sleep mode register 1"),
            bit_size: 32,
            fields: &[
                Field {
                    name: "tim2smen",
                    description: Some("TIM2 timer clock enable during Sleep mode"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "tim3smen",
                    description: Some("TIM3 timer clock enable during Sleep mode"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 1 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "tim4smen",
                    description: Some("TIM4 timer clock enable during Sleep mode"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 2 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "tim6smen",
                    description: Some("TIM6 timer clock enable during Sleep mode"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 4 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "tim7smen",
                    description: Some("TIM7 timer clock enable during Sleep mode"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 5 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "lpuart2smen",
                    description: Some("LPUART2 clock enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 7 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "usart5smen",
                    description: Some("USART5 clock enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 8 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "usart6smen",
                    description: Some("USART6 clock enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 9 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "rtcapbsmen",
                    description: Some("RTC APB clock enable during Sleep mode"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 10 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "wwdgsmen",
                    description: Some("WWDG clock enable during Sleep mode"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 11 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "fdcansmen",
                    description: Some("FDCAN clock enable during Sleep mode"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 12 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "usbsmen",
                    description: Some("USB clock enable during Sleep mode"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 13 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "spi2smen",
                    description: Some("SPI2 clock enable during Sleep mode"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 14 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "spi3smen",
                    description: Some("SPI3 clock enable during Sleep mode"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 15 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "crsssmen",
                    description: Some("CRSS clock enable during Sleep mode"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 16 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "usart2smen",
                    description: Some("USART2 clock enable during Sleep mode"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 17 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "usart3smen",
                    description: Some("USART3 clock enable during Sleep mode"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 18 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "usart4smen",
                    description: Some("USART4 clock enable during Sleep mode"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 19 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "lpuart1smen",
                    description: Some("LPUART1 clock enable during Sleep mode"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 20 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "i2c1smen",
                    description: Some("I2C1 clock enable during Sleep mode"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 21 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "i2c2smen",
                    description: Some("I2C2 clock enable during Sleep mode"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 22 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "i2c3smen",
                    description: Some("I2C3 clock enable during Sleep mode"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 23 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "cecsmen",
                    description: Some("HDMI CEC clock enable during Sleep mode"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 24 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "ucpd1smen",
                    description: Some("UCPD1 clock enable during Sleep mode"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 25 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "ucpd2smen",
                    description: Some("UCPD2 clock enable during Sleep mode"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 26 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "dbgsmen",
                    description: Some("Debug support clock enable during Sleep mode"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 27 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "pwrsmen",
                    description: Some("Power interface clock enable during Sleep mode"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 28 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "dac1smen",
                    description: Some("DAC1 interface clock enable during Sleep mode"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 29 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "lptim2smen",
                    description: Some("Low Power Timer 2 clock enable during Sleep mode"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 30 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "lptim1smen",
                    description: Some("Low Power Timer 1 clock enable during Sleep mode"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 31 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
            ],
        },
        FieldSet {
            name: "Apbsmenr2",
            extends: None,
            description: Some("APB peripheral clock enable in Sleep mode register 2"),
            bit_size: 32,
            fields: &[
                Field {
                    name: "syscfgsmen",
                    description: Some("SYSCFG, COMP and VREFBUF clock enable during Sleep mode"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "tim1smen",
                    description: Some("TIM1 timer clock enable during Sleep mode"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 11 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "spi1smen",
                    description: Some("SPI1 clock enable during Sleep mode"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 12 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "usart1smen",
                    description: Some("USART1 clock enable during Sleep mode"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 14 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "tim14smen",
                    description: Some("TIM14 timer clock enable during Sleep mode"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 15 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "tim15smen",
                    description: Some("TIM15 timer clock enable during Sleep mode"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 16 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "tim16smen",
                    description: Some("TIM16 timer clock enable during Sleep mode"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 17 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "tim17smen",
                    description: Some("TIM16 timer clock enable during Sleep mode"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 18 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "adcsmen",
                    description: Some("ADC clock enable during Sleep mode"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 20 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
            ],
        },
        FieldSet {
            name: "Bdcr",
            extends: None,
            description: Some("RTC domain control register"),
            bit_size: 32,
            fields: &[
                Field {
                    name: "lseon",
                    description: Some("LSE oscillator enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "lserdy",
                    description: Some("LSE oscillator ready"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 1 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "lsebyp",
                    description: Some("LSE oscillator bypass"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 2 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "lsedrv",
                    description: Some("LSE oscillator drive capability"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 3 }),
                    bit_size: 2,
                    array: None,
                    enumm: Some("Lsedrv"),
                },
                Field {
                    name: "lsecsson",
                    description: Some("CSS on LSE enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 5 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "lsecssd",
                    description: Some("CSS on LSE failure Detection"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 6 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "rtcsel",
                    description: Some("RTC clock source selection"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 8 }),
                    bit_size: 2,
                    array: None,
                    enumm: Some("Rtcsel"),
                },
                Field {
                    name: "rtcen",
                    description: Some("RTC clock enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 15 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "bdrst",
                    description: Some("RTC domain software reset"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 16 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "lscoen",
                    description: Some("Low-speed clock output (LSCO) enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 24 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "lscosel",
                    description: Some("Low-speed clock output selection"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 25 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
            ],
        },
        FieldSet {
            name: "Ccipr",
            extends: None,
            description: Some("Peripherals independent clock configuration register"),
            bit_size: 32,
            fields: &[
                Field {
                    name: "usart1sel",
                    description: Some("USART1 clock source selection"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
                    bit_size: 2,
                    array: None,
                    enumm: Some("Usartsel"),
                },
                Field {
                    name: "usart2sel",
                    description: Some("USART2 clock source selection"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 2 }),
                    bit_size: 2,
                    array: None,
                    enumm: Some("Usartsel"),
                },
                Field {
                    name: "usart3sel",
                    description: Some("USART3 clock source selection"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 4 }),
                    bit_size: 2,
                    array: None,
                    enumm: Some("Usartsel"),
                },
                Field {
                    name: "cecsel",
                    description: Some("HDMI CEC clock source selection"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 6 }),
                    bit_size: 1,
                    array: None,
                    enumm: Some("Cecsel"),
                },
                Field {
                    name: "lpuart2sel",
                    description: Some("LPUART2 clock source selection"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 8 }),
                    bit_size: 2,
                    array: None,
                    enumm: Some("Lpuart2sel"),
                },
                Field {
                    name: "lpuart1sel",
                    description: Some("LPUART1 clock source selection"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 10 }),
                    bit_size: 2,
                    array: None,
                    enumm: Some("Lpuart1sel"),
                },
                Field {
                    name: "i2c1sel",
                    description: Some("I2C1 clock source selection"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 12 }),
                    bit_size: 2,
                    array: None,
                    enumm: Some("I2c1sel"),
                },
                Field {
                    name: "i2c2i2s1sel",
                    description: Some("I2C2 or I2S1 clock source selection"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 14 }),
                    bit_size: 2,
                    array: None,
                    enumm: Some("I2c2i2s1sel"),
                },
                Field {
                    name: "lptim1sel",
                    description: Some("LPTIM1 clock source selection"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 18 }),
                    bit_size: 2,
                    array: None,
                    enumm: Some("Lptim1sel"),
                },
                Field {
                    name: "lptim2sel",
                    description: Some("LPTIM2 clock source selection"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 20 }),
                    bit_size: 2,
                    array: None,
                    enumm: Some("Lptim2sel"),
                },
                Field {
                    name: "tim1sel",
                    description: Some("TIM1 clock source selection"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 22 }),
                    bit_size: 1,
                    array: None,
                    enumm: Some("Tim1sel"),
                },
                Field {
                    name: "tim15sel",
                    description: Some("TIM15 clock source selection"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 24 }),
                    bit_size: 1,
                    array: None,
                    enumm: Some("Tim15sel"),
                },
                Field {
                    name: "rngsel",
                    description: Some("RNG clock source selection"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 26 }),
                    bit_size: 2,
                    array: None,
                    enumm: Some("Rngsel"),
                },
                Field {
                    name: "rngdiv",
                    description: Some("Division factor of RNG clock divider"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 28 }),
                    bit_size: 2,
                    array: None,
                    enumm: Some("Rngdiv"),
                },
                Field {
                    name: "adcsel",
                    description: Some("ADCs clock source selection"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 30 }),
                    bit_size: 2,
                    array: None,
                    enumm: Some("Adcsel"),
                },
            ],
        },
        FieldSet {
            name: "Ccipr2",
            extends: None,
            description: Some("Peripherals independent clock configuration register 2"),
            bit_size: 32,
            fields: &[
                Field {
                    name: "i2s1sel",
                    description: Some("I2S1SEL"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
                    bit_size: 2,
                    array: None,
                    enumm: Some("I2s1sel"),
                },
                Field {
                    name: "i2s2sel",
                    description: Some("I2S2SEL"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 2 }),
                    bit_size: 2,
                    array: None,
                    enumm: Some("I2s2sel"),
                },
                Field {
                    name: "fdcansel",
                    description: Some("FDCANSEL"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 8 }),
                    bit_size: 2,
                    array: None,
                    enumm: Some("Fdcansel"),
                },
                Field {
                    name: "usbsel",
                    description: Some("USBSEL"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 12 }),
                    bit_size: 2,
                    array: None,
                    enumm: Some("Usbsel"),
                },
            ],
        },
        FieldSet {
            name: "Cfgr",
            extends: None,
            description: Some("Clock configuration register"),
            bit_size: 32,
            fields: &[
                Field {
                    name: "sw",
                    description: Some("System clock switch"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
                    bit_size: 3,
                    array: None,
                    enumm: Some("Sw"),
                },
                Field {
                    name: "sws",
                    description: Some("System clock switch status"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 3 }),
                    bit_size: 3,
                    array: None,
                    enumm: Some("Sw"),
                },
                Field {
                    name: "hpre",
                    description: Some("AHB prescaler"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 8 }),
                    bit_size: 4,
                    array: None,
                    enumm: Some("Hpre"),
                },
                Field {
                    name: "ppre",
                    description: Some("APB prescaler"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 12 }),
                    bit_size: 3,
                    array: None,
                    enumm: Some("Ppre"),
                },
                Field {
                    name: "mco2sel",
                    description: Some("MCO2SEL"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 16 }),
                    bit_size: 4,
                    array: None,
                    enumm: Some("Mcosel"),
                },
                Field {
                    name: "mco2pre",
                    description: Some("MCO2PRE"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 20 }),
                    bit_size: 4,
                    array: None,
                    enumm: Some("Mcopre"),
                },
                Field {
                    name: "mco1sel",
                    description: Some("Microcontroller clock output"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 24 }),
                    bit_size: 4,
                    array: None,
                    enumm: Some("Mcosel"),
                },
                Field {
                    name: "mco1pre",
                    description: Some("Microcontroller clock output prescaler"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 28 }),
                    bit_size: 4,
                    array: None,
                    enumm: Some("Mcopre"),
                },
            ],
        },
        FieldSet {
            name: "Cicr",
            extends: None,
            description: Some("Clock interrupt clear register"),
            bit_size: 32,
            fields: &[
                Field {
                    name: "lsirdyc",
                    description: Some("LSI ready interrupt clear"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "lserdyc",
                    description: Some("LSE ready interrupt clear"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 1 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "hsi48rdyc",
                    description: Some("HSI48RDYC"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 2 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "hsirdyc",
                    description: Some("HSI ready interrupt clear"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 3 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "hserdyc",
                    description: Some("HSE ready interrupt clear"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 4 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "pllsysrdyc",
                    description: Some("PLL ready interrupt clear"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 5 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "cssc",
                    description: Some("Clock security system interrupt clear"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 8 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "lsecssc",
                    description: Some("LSE Clock security system interrupt clear"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 9 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
            ],
        },
        FieldSet {
            name: "Cier",
            extends: None,
            description: Some("Clock interrupt enable register"),
            bit_size: 32,
            fields: &[
                Field {
                    name: "lsirdyie",
                    description: Some("LSI ready interrupt enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "lserdyie",
                    description: Some("LSE ready interrupt enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 1 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "hsirdyie",
                    description: Some("HSI ready interrupt enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 3 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "hserdyie",
                    description: Some("HSE ready interrupt enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 4 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "pllsysrdyie",
                    description: Some("PLL ready interrupt enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 5 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
            ],
        },
        FieldSet {
            name: "Cifr",
            extends: None,
            description: Some("Clock interrupt flag register"),
            bit_size: 32,
            fields: &[
                Field {
                    name: "lsirdyf",
                    description: Some("LSI ready interrupt flag"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "lserdyf",
                    description: Some("LSE ready interrupt flag"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 1 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "hsi48rdyf",
                    description: Some("HSI48RDYF"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 2 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "hsirdyf",
                    description: Some("HSI ready interrupt flag"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 3 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "hserdyf",
                    description: Some("HSE ready interrupt flag"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 4 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "pllsysrdyf",
                    description: Some("PLL ready interrupt flag"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 5 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "cssf",
                    description: Some("Clock security system interrupt flag"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 8 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "lsecssf",
                    description: Some("LSE Clock security system interrupt flag"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 9 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
            ],
        },
        FieldSet {
            name: "Cr",
            extends: None,
            description: Some("Clock control register"),
            bit_size: 32,
            fields: &[
                Field {
                    name: "hsion",
                    description: Some("HSI clock enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 8 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "hsikeron",
                    description: Some("HSI always enable for peripheral kernels"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 9 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "hsirdy",
                    description: Some("HSI clock ready flag"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 10 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "hsidiv",
                    description: Some("HSI clock division factor"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 11 }),
                    bit_size: 3,
                    array: None,
                    enumm: Some("Hsidiv"),
                },
                Field {
                    name: "hseon",
                    description: Some("HSE clock enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 16 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "hserdy",
                    description: Some("HSE clock ready flag"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 17 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "hsebyp",
                    description: Some("HSE crystal oscillator bypass"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 18 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "csson",
                    description: Some("Clock security system enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 19 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "hsi48on",
                    description: Some("HSI48ON"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 22 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "hsi48rdy",
                    description: Some("HSI48RDY"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 23 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "pllon",
                    description: Some("PLL enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 24 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "pllrdy",
                    description: Some("PLL clock ready flag"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 25 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
            ],
        },
        FieldSet {
            name: "Crrcr",
            extends: None,
            description: Some("RCC clock recovery RC register"),
            bit_size: 32,
            fields: &[Field {
                name: "hsi48cal",
                description: Some("HSI48 clock calibration"),
                bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
                bit_size: 9,
                array: None,
                enumm: None,
            }],
        },
        FieldSet {
            name: "Csr",
            extends: None,
            description: Some("Control/status register"),
            bit_size: 32,
            fields: &[
                Field {
                    name: "lsion",
                    description: Some("LSI oscillator enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "lsirdy",
                    description: Some("LSI oscillator ready"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 1 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "rmvf",
                    description: Some("Remove reset flags"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 23 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "oblrstf",
                    description: Some("Option byte loader reset flag"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 25 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "pinrstf",
                    description: Some("Pin reset flag"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 26 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "pwrrstf",
                    description: Some("BOR or POR/PDR flag"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 27 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "sftrstf",
                    description: Some("Software reset flag"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 28 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "iwdgrstf",
                    description: Some("Independent window watchdog reset flag"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 29 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "wwdgrstf",
                    description: Some("Window watchdog reset flag"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 30 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "lpwrrstf",
                    description: Some("Low-power reset flag"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 31 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
            ],
        },
        FieldSet {
            name: "Gpioenr",
            extends: None,
            description: Some("GPIO clock enable register"),
            bit_size: 32,
            fields: &[
                Field {
                    name: "gpioaen",
                    description: Some("I/O port A clock enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "gpioben",
                    description: Some("I/O port B clock enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 1 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "gpiocen",
                    description: Some("I/O port C clock enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 2 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "gpioden",
                    description: Some("I/O port D clock enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 3 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "gpiofen",
                    description: Some("I/O port F clock enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 5 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
            ],
        },
        FieldSet {
            name: "Gpiorstr",
            extends: None,
            description: Some("GPIO reset register"),
            bit_size: 32,
            fields: &[
                Field {
                    name: "gpioarst",
                    description: Some("I/O port A reset"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "gpiobrst",
                    description: Some("I/O port B reset"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 1 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "gpiocrst",
                    description: Some("I/O port C reset"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 2 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "gpiodrst",
                    description: Some("I/O port D reset"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 3 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "gpiofrst",
                    description: Some("I/O port F reset"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 5 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
            ],
        },
        FieldSet {
            name: "Gpiosmenr",
            extends: None,
            description: Some("GPIO in Sleep mode clock enable register"),
            bit_size: 32,
            fields: &[
                Field {
                    name: "gpioasmen",
                    description: Some("I/O port A clock enable during Sleep mode"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "gpiobsmen",
                    description: Some("I/O port B clock enable during Sleep mode"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 1 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "gpiocsmen",
                    description: Some("I/O port C clock enable during Sleep mode"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 2 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "gpiodsmen",
                    description: Some("I/O port D clock enable during Sleep mode"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 3 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "gpiofsmen",
                    description: Some("I/O port F clock enable during Sleep mode"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 5 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
            ],
        },
        FieldSet {
            name: "Icscr",
            extends: None,
            description: Some("Internal clock sources calibration register"),
            bit_size: 32,
            fields: &[
                Field {
                    name: "hsical",
                    description: Some("HSI clock calibration"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
                    bit_size: 8,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "hsitrim",
                    description: Some("HSI clock trimming"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 8 }),
                    bit_size: 7,
                    array: None,
                    enumm: None,
                },
            ],
        },
        FieldSet {
            name: "Pllcfgr",
            extends: None,
            description: Some("PLL configuration register"),
            bit_size: 32,
            fields: &[
                Field {
                    name: "pllsrc",
                    description: Some("PLL input clock source"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
                    bit_size: 2,
                    array: None,
                    enumm: Some("Pllsrc"),
                },
                Field {
                    name: "pllm",
                    description: Some("Division factor M of the PLL input clock divider"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 4 }),
                    bit_size: 3,
                    array: None,
                    enumm: Some("Pllm"),
                },
                Field {
                    name: "plln",
                    description: Some("PLL frequency multiplication factor N"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 8 }),
                    bit_size: 7,
                    array: None,
                    enumm: Some("Plln"),
                },
                Field {
                    name: "pllpen",
                    description: Some("PLLPCLK clock output enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 16 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "pllp",
                    description: Some("PLL VCO division factor P for PLLPCLK clock output"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 17 }),
                    bit_size: 5,
                    array: None,
                    enumm: Some("Pllp"),
                },
                Field {
                    name: "pllqen",
                    description: Some("PLLQCLK clock output enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 24 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "pllq",
                    description: Some("PLL VCO division factor Q for PLLQCLK clock output"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 25 }),
                    bit_size: 3,
                    array: None,
                    enumm: Some("Pllq"),
                },
                Field {
                    name: "pllren",
                    description: Some("PLLRCLK clock output enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 28 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "pllr",
                    description: Some("PLL VCO division factor R for PLLRCLK clock output"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 29 }),
                    bit_size: 3,
                    array: None,
                    enumm: Some("Pllr"),
                },
            ],
        },
    ],
    enums: &[
        Enum {
            name: "Adcsel",
            description: None,
            bit_size: 2,
            variants: &[
                EnumVariant {
                    name: "SYS",
                    description: Some("SYSCLK used as ADC clock source"),
                    value: 0,
                },
                EnumVariant {
                    name: "PLL1_P",
                    description: Some("PLLPCLK used as ADC clock source"),
                    value: 1,
                },
                EnumVariant {
                    name: "HSI",
                    description: Some("HSI used as ADC clock source"),
                    value: 2,
                },
            ],
        },
        Enum {
            name: "Cecsel",
            description: None,
            bit_size: 1,
            variants: &[
                EnumVariant {
                    name: "HSI_DIV_488",
                    description: Some("HSI divided by 488 used as CEC clock"),
                    value: 0,
                },
                EnumVariant {
                    name: "LSE",
                    description: Some("LSE used as CEC clock"),
                    value: 1,
                },
            ],
        },
        Enum {
            name: "Fdcansel",
            description: None,
            bit_size: 2,
            variants: &[
                EnumVariant {
                    name: "PCLK1",
                    description: Some("PCLK used as FDCAN clock source"),
                    value: 0,
                },
                EnumVariant {
                    name: "PLL1_Q",
                    description: Some("PLLQCLK used as FDCAN clock source"),
                    value: 1,
                },
                EnumVariant {
                    name: "HSE",
                    description: Some("HSE used as FDCAN clock source"),
                    value: 2,
                },
            ],
        },
        Enum {
            name: "Hpre",
            description: None,
            bit_size: 4,
            variants: &[
                EnumVariant {
                    name: "DIV1",
                    description: Some("SYSCLK not divided"),
                    value: 0,
                },
                EnumVariant {
                    name: "DIV2",
                    description: Some("SYSCLK is divided by 2"),
                    value: 8,
                },
                EnumVariant {
                    name: "DIV4",
                    description: Some("SYSCLK is divided by 4"),
                    value: 9,
                },
                EnumVariant {
                    name: "DIV8",
                    description: Some("SYSCLK is divided by 8"),
                    value: 10,
                },
                EnumVariant {
                    name: "DIV16",
                    description: Some("SYSCLK is divided by 16"),
                    value: 11,
                },
                EnumVariant {
                    name: "DIV64",
                    description: Some("SYSCLK is divided by 64"),
                    value: 12,
                },
                EnumVariant {
                    name: "DIV128",
                    description: Some("SYSCLK is divided by 128"),
                    value: 13,
                },
                EnumVariant {
                    name: "DIV256",
                    description: Some("SYSCLK is divided by 256"),
                    value: 14,
                },
                EnumVariant {
                    name: "DIV512",
                    description: Some("SYSCLK is divided by 512"),
                    value: 15,
                },
            ],
        },
        Enum {
            name: "Hsidiv",
            description: None,
            bit_size: 3,
            variants: &[
                EnumVariant {
                    name: "DIV1",
                    description: Some("HSI clock is not divided"),
                    value: 0,
                },
                EnumVariant {
                    name: "DIV2",
                    description: Some("HSI clock is divided by 2"),
                    value: 1,
                },
                EnumVariant {
                    name: "DIV4",
                    description: Some("HSI clock is divided by 4"),
                    value: 2,
                },
                EnumVariant {
                    name: "DIV8",
                    description: Some("HSI clock is divided by 8"),
                    value: 3,
                },
                EnumVariant {
                    name: "DIV16",
                    description: Some("HSI clock is divided by 16"),
                    value: 4,
                },
                EnumVariant {
                    name: "DIV32",
                    description: Some("HSI clock is divided by 32"),
                    value: 5,
                },
                EnumVariant {
                    name: "DIV64",
                    description: Some("HSI clock is divided by 64"),
                    value: 6,
                },
                EnumVariant {
                    name: "DIV128",
                    description: Some("HSI clock is divided by 128"),
                    value: 7,
                },
            ],
        },
        Enum {
            name: "I2c1sel",
            description: None,
            bit_size: 2,
            variants: &[
                EnumVariant {
                    name: "PCLK1",
                    description: Some("PCLK used as I2C1 clock source"),
                    value: 0,
                },
                EnumVariant {
                    name: "SYS",
                    description: Some("SYSCLK used as I2C1 clock source"),
                    value: 1,
                },
                EnumVariant {
                    name: "HSI",
                    description: Some("HSI used as I2C1 clock source"),
                    value: 2,
                },
            ],
        },
        Enum {
            name: "I2c2i2s1sel",
            description: None,
            bit_size: 2,
            variants: &[
                EnumVariant {
                    name: "PCLK1",
                    description: Some("PCLK used as I2C2/I2S2 clock source"),
                    value: 0,
                },
                EnumVariant {
                    name: "SYS",
                    description: Some("SYSCLK used as I2C2/I2S2 clock source"),
                    value: 1,
                },
                EnumVariant {
                    name: "HSI",
                    description: Some("HSI used as I2C2/I2S2 clock source"),
                    value: 2,
                },
                EnumVariant {
                    name: "I2S_CKIN",
                    description: Some("External clock used as I2C2/I2S2 clock source"),
                    value: 3,
                },
            ],
        },
        Enum {
            name: "I2s1sel",
            description: None,
            bit_size: 2,
            variants: &[
                EnumVariant {
                    name: "SYS",
                    description: Some("SYSCLK used as I2S1 clock source"),
                    value: 0,
                },
                EnumVariant {
                    name: "PLL1_P",
                    description: Some("PLLPCLK used as I2S1 clock source"),
                    value: 1,
                },
                EnumVariant {
                    name: "HSI",
                    description: Some("HSI used as I2S1 clock source"),
                    value: 2,
                },
                EnumVariant {
                    name: "I2S_CKIN",
                    description: Some("External clock used as I2S1 clock source"),
                    value: 3,
                },
            ],
        },
        Enum {
            name: "I2s2sel",
            description: None,
            bit_size: 2,
            variants: &[
                EnumVariant {
                    name: "SYS",
                    description: Some("SYSCLK used as I2S2 clock source"),
                    value: 0,
                },
                EnumVariant {
                    name: "PLL1_P",
                    description: Some("PLLPCLK used as I2S2 clock source"),
                    value: 1,
                },
                EnumVariant {
                    name: "HSI",
                    description: Some("HSI used as I2S2 clock source"),
                    value: 2,
                },
                EnumVariant {
                    name: "I2S_CKIN",
                    description: Some("External clock used as I2S2 clock source"),
                    value: 3,
                },
            ],
        },
        Enum {
            name: "Lptim1sel",
            description: None,
            bit_size: 2,
            variants: &[
                EnumVariant {
                    name: "PCLK1",
                    description: Some("PCLK used as LPTIM1 clock source"),
                    value: 0,
                },
                EnumVariant {
                    name: "LSI",
                    description: Some("LSI used as LPTIM1 clock source"),
                    value: 1,
                },
                EnumVariant {
                    name: "HSI",
                    description: Some("HSI used as LPTIM1 clock source"),
                    value: 2,
                },
                EnumVariant {
                    name: "LSE",
                    description: Some("LSE used as LPTIM1 clock source"),
                    value: 3,
                },
            ],
        },
        Enum {
            name: "Lptim2sel",
            description: None,
            bit_size: 2,
            variants: &[
                EnumVariant {
                    name: "PCLK1",
                    description: Some("PCLK used as LPTIM2 clock source"),
                    value: 0,
                },
                EnumVariant {
                    name: "LSI",
                    description: Some("LSI used as LPTIM2 clock source"),
                    value: 1,
                },
                EnumVariant {
                    name: "HSI",
                    description: Some("HSI used as LPTIM2 clock source"),
                    value: 2,
                },
                EnumVariant {
                    name: "LSE",
                    description: Some("LSE used as LPTIM2 clock source"),
                    value: 3,
                },
            ],
        },
        Enum {
            name: "Lpuart1sel",
            description: None,
            bit_size: 2,
            variants: &[
                EnumVariant {
                    name: "PCLK1",
                    description: Some("PCLK used as LPUART1 clock source"),
                    value: 0,
                },
                EnumVariant {
                    name: "SYS",
                    description: Some("SYSCLK used as LPUART1 clock source"),
                    value: 1,
                },
                EnumVariant {
                    name: "HSI",
                    description: Some("HSI used as LPUART1 clock source"),
                    value: 2,
                },
                EnumVariant {
                    name: "LSE",
                    description: Some("LSE used as LPUART1 clock source"),
                    value: 3,
                },
            ],
        },
        Enum {
            name: "Lpuart2sel",
            description: None,
            bit_size: 2,
            variants: &[
                EnumVariant {
                    name: "PCLK1",
                    description: Some("PCLK used as LPUART2 clock source"),
                    value: 0,
                },
                EnumVariant {
                    name: "SYS",
                    description: Some("SYSCLK used as LPUART2 clock source"),
                    value: 1,
                },
                EnumVariant {
                    name: "HSI",
                    description: Some("HSI used as LPUART2 clock source"),
                    value: 2,
                },
                EnumVariant {
                    name: "LSE",
                    description: Some("LSE used as LPUART2 clock source"),
                    value: 3,
                },
            ],
        },
        Enum {
            name: "Lsedrv",
            description: None,
            bit_size: 2,
            variants: &[
                EnumVariant {
                    name: "LOW",
                    description: Some("Low driving capability"),
                    value: 0,
                },
                EnumVariant {
                    name: "MEDIUM_LOW",
                    description: Some("Medium low driving capability"),
                    value: 1,
                },
                EnumVariant {
                    name: "MEDIUM_HIGH",
                    description: Some("Medium high driving capability"),
                    value: 2,
                },
                EnumVariant {
                    name: "HIGH",
                    description: Some("High driving capability"),
                    value: 3,
                },
            ],
        },
        Enum {
            name: "Mcopre",
            description: None,
            bit_size: 4,
            variants: &[
                EnumVariant {
                    name: "DIV1",
                    description: Some("MCO1 not divided"),
                    value: 0,
                },
                EnumVariant {
                    name: "DIV2",
                    description: Some("MCO clock is divided by 2"),
                    value: 1,
                },
                EnumVariant {
                    name: "DIV4",
                    description: Some("MCO clock is divided by 4"),
                    value: 2,
                },
                EnumVariant {
                    name: "DIV8",
                    description: Some("MCO clock is divided by 8"),
                    value: 3,
                },
                EnumVariant {
                    name: "DIV16",
                    description: Some("MCO clock is divided divided by 16"),
                    value: 4,
                },
                EnumVariant {
                    name: "DIV32",
                    description: Some("MCO clock is divided divided by 32"),
                    value: 5,
                },
                EnumVariant {
                    name: "DIV64",
                    description: Some("MCO clock is divided divided by 64"),
                    value: 6,
                },
                EnumVariant {
                    name: "DIV128",
                    description: Some("MCO clock is divided divided by 128"),
                    value: 7,
                },
                EnumVariant {
                    name: "DIV256",
                    description: Some("MCO clock is divided divided by 256"),
                    value: 8,
                },
                EnumVariant {
                    name: "DIV512",
                    description: Some("MCO clock is divided divided by 512"),
                    value: 9,
                },
                EnumVariant {
                    name: "DIV1024",
                    description: Some("MCO clock is divided divided by 1024"),
                    value: 10,
                },
            ],
        },
        Enum {
            name: "Mcosel",
            description: None,
            bit_size: 4,
            variants: &[
                EnumVariant {
                    name: "DISABLE",
                    description: Some("No clock, MCO output disabled"),
                    value: 0,
                },
                EnumVariant {
                    name: "SYS",
                    description: Some("SYSCLK selected as MCO source"),
                    value: 1,
                },
                EnumVariant {
                    name: "HSI48",
                    description: Some("HSI48 selected as MCO source"),
                    value: 2,
                },
                EnumVariant {
                    name: "HSI",
                    description: Some("HSI selected as MCO source"),
                    value: 3,
                },
                EnumVariant {
                    name: "HSE",
                    description: Some("HSE selected as MCO source"),
                    value: 4,
                },
                EnumVariant {
                    name: "PLLRCLK",
                    description: Some("PLLRCLK selected as MCO source"),
                    value: 5,
                },
                EnumVariant {
                    name: "LSI",
                    description: Some("LSI selected as MCO source"),
                    value: 6,
                },
                EnumVariant {
                    name: "LSE",
                    description: Some("LSE selected as MCO source"),
                    value: 7,
                },
                EnumVariant {
                    name: "PLL1_P",
                    description: Some("PLLPCLK selected as MCO source"),
                    value: 8,
                },
                EnumVariant {
                    name: "PLL1_Q",
                    description: Some("PLLQCLK selected as MCO source"),
                    value: 9,
                },
                EnumVariant {
                    name: "RTCCLK",
                    description: Some("RTCCLK selected as MCO source"),
                    value: 10,
                },
                EnumVariant {
                    name: "RTC_WKUP",
                    description: Some("RTC_Wakeup selected as MCO source"),
                    value: 11,
                },
            ],
        },
        Enum {
            name: "Pllm",
            description: None,
            bit_size: 3,
            variants: &[
                EnumVariant {
                    name: "DIV1",
                    description: None,
                    value: 0,
                },
                EnumVariant {
                    name: "DIV2",
                    description: None,
                    value: 1,
                },
                EnumVariant {
                    name: "DIV3",
                    description: None,
                    value: 2,
                },
                EnumVariant {
                    name: "DIV4",
                    description: None,
                    value: 3,
                },
                EnumVariant {
                    name: "DIV5",
                    description: None,
                    value: 4,
                },
                EnumVariant {
                    name: "DIV6",
                    description: None,
                    value: 5,
                },
                EnumVariant {
                    name: "DIV7",
                    description: None,
                    value: 6,
                },
                EnumVariant {
                    name: "DIV8",
                    description: None,
                    value: 7,
                },
            ],
        },
        Enum {
            name: "Plln",
            description: None,
            bit_size: 7,
            variants: &[
                EnumVariant {
                    name: "MUL8",
                    description: None,
                    value: 8,
                },
                EnumVariant {
                    name: "MUL9",
                    description: None,
                    value: 9,
                },
                EnumVariant {
                    name: "MUL10",
                    description: None,
                    value: 10,
                },
                EnumVariant {
                    name: "MUL11",
                    description: None,
                    value: 11,
                },
                EnumVariant {
                    name: "MUL12",
                    description: None,
                    value: 12,
                },
                EnumVariant {
                    name: "MUL13",
                    description: None,
                    value: 13,
                },
                EnumVariant {
                    name: "MUL14",
                    description: None,
                    value: 14,
                },
                EnumVariant {
                    name: "MUL15",
                    description: None,
                    value: 15,
                },
                EnumVariant {
                    name: "MUL16",
                    description: None,
                    value: 16,
                },
                EnumVariant {
                    name: "MUL17",
                    description: None,
                    value: 17,
                },
                EnumVariant {
                    name: "MUL18",
                    description: None,
                    value: 18,
                },
                EnumVariant {
                    name: "MUL19",
                    description: None,
                    value: 19,
                },
                EnumVariant {
                    name: "MUL20",
                    description: None,
                    value: 20,
                },
                EnumVariant {
                    name: "MUL21",
                    description: None,
                    value: 21,
                },
                EnumVariant {
                    name: "MUL22",
                    description: None,
                    value: 22,
                },
                EnumVariant {
                    name: "MUL23",
                    description: None,
                    value: 23,
                },
                EnumVariant {
                    name: "MUL24",
                    description: None,
                    value: 24,
                },
                EnumVariant {
                    name: "MUL25",
                    description: None,
                    value: 25,
                },
                EnumVariant {
                    name: "MUL26",
                    description: None,
                    value: 26,
                },
                EnumVariant {
                    name: "MUL27",
                    description: None,
                    value: 27,
                },
                EnumVariant {
                    name: "MUL28",
                    description: None,
                    value: 28,
                },
                EnumVariant {
                    name: "MUL29",
                    description: None,
                    value: 29,
                },
                EnumVariant {
                    name: "MUL30",
                    description: None,
                    value: 30,
                },
                EnumVariant {
                    name: "MUL31",
                    description: None,
                    value: 31,
                },
                EnumVariant {
                    name: "MUL32",
                    description: None,
                    value: 32,
                },
                EnumVariant {
                    name: "MUL33",
                    description: None,
                    value: 33,
                },
                EnumVariant {
                    name: "MUL34",
                    description: None,
                    value: 34,
                },
                EnumVariant {
                    name: "MUL35",
                    description: None,
                    value: 35,
                },
                EnumVariant {
                    name: "MUL36",
                    description: None,
                    value: 36,
                },
                EnumVariant {
                    name: "MUL37",
                    description: None,
                    value: 37,
                },
                EnumVariant {
                    name: "MUL38",
                    description: None,
                    value: 38,
                },
                EnumVariant {
                    name: "MUL39",
                    description: None,
                    value: 39,
                },
                EnumVariant {
                    name: "MUL40",
                    description: None,
                    value: 40,
                },
                EnumVariant {
                    name: "MUL41",
                    description: None,
                    value: 41,
                },
                EnumVariant {
                    name: "MUL42",
                    description: None,
                    value: 42,
                },
                EnumVariant {
                    name: "MUL43",
                    description: None,
                    value: 43,
                },
                EnumVariant {
                    name: "MUL44",
                    description: None,
                    value: 44,
                },
                EnumVariant {
                    name: "MUL45",
                    description: None,
                    value: 45,
                },
                EnumVariant {
                    name: "MUL46",
                    description: None,
                    value: 46,
                },
                EnumVariant {
                    name: "MUL47",
                    description: None,
                    value: 47,
                },
                EnumVariant {
                    name: "MUL48",
                    description: None,
                    value: 48,
                },
                EnumVariant {
                    name: "MUL49",
                    description: None,
                    value: 49,
                },
                EnumVariant {
                    name: "MUL50",
                    description: None,
                    value: 50,
                },
                EnumVariant {
                    name: "MUL51",
                    description: None,
                    value: 51,
                },
                EnumVariant {
                    name: "MUL52",
                    description: None,
                    value: 52,
                },
                EnumVariant {
                    name: "MUL53",
                    description: None,
                    value: 53,
                },
                EnumVariant {
                    name: "MUL54",
                    description: None,
                    value: 54,
                },
                EnumVariant {
                    name: "MUL55",
                    description: None,
                    value: 55,
                },
                EnumVariant {
                    name: "MUL56",
                    description: None,
                    value: 56,
                },
                EnumVariant {
                    name: "MUL57",
                    description: None,
                    value: 57,
                },
                EnumVariant {
                    name: "MUL58",
                    description: None,
                    value: 58,
                },
                EnumVariant {
                    name: "MUL59",
                    description: None,
                    value: 59,
                },
                EnumVariant {
                    name: "MUL60",
                    description: None,
                    value: 60,
                },
                EnumVariant {
                    name: "MUL61",
                    description: None,
                    value: 61,
                },
                EnumVariant {
                    name: "MUL62",
                    description: None,
                    value: 62,
                },
                EnumVariant {
                    name: "MUL63",
                    description: None,
                    value: 63,
                },
                EnumVariant {
                    name: "MUL64",
                    description: None,
                    value: 64,
                },
                EnumVariant {
                    name: "MUL65",
                    description: None,
                    value: 65,
                },
                EnumVariant {
                    name: "MUL66",
                    description: None,
                    value: 66,
                },
                EnumVariant {
                    name: "MUL67",
                    description: None,
                    value: 67,
                },
                EnumVariant {
                    name: "MUL68",
                    description: None,
                    value: 68,
                },
                EnumVariant {
                    name: "MUL69",
                    description: None,
                    value: 69,
                },
                EnumVariant {
                    name: "MUL70",
                    description: None,
                    value: 70,
                },
                EnumVariant {
                    name: "MUL71",
                    description: None,
                    value: 71,
                },
                EnumVariant {
                    name: "MUL72",
                    description: None,
                    value: 72,
                },
                EnumVariant {
                    name: "MUL73",
                    description: None,
                    value: 73,
                },
                EnumVariant {
                    name: "MUL74",
                    description: None,
                    value: 74,
                },
                EnumVariant {
                    name: "MUL75",
                    description: None,
                    value: 75,
                },
                EnumVariant {
                    name: "MUL76",
                    description: None,
                    value: 76,
                },
                EnumVariant {
                    name: "MUL77",
                    description: None,
                    value: 77,
                },
                EnumVariant {
                    name: "MUL78",
                    description: None,
                    value: 78,
                },
                EnumVariant {
                    name: "MUL79",
                    description: None,
                    value: 79,
                },
                EnumVariant {
                    name: "MUL80",
                    description: None,
                    value: 80,
                },
                EnumVariant {
                    name: "MUL81",
                    description: None,
                    value: 81,
                },
                EnumVariant {
                    name: "MUL82",
                    description: None,
                    value: 82,
                },
                EnumVariant {
                    name: "MUL83",
                    description: None,
                    value: 83,
                },
                EnumVariant {
                    name: "MUL84",
                    description: None,
                    value: 84,
                },
                EnumVariant {
                    name: "MUL85",
                    description: None,
                    value: 85,
                },
                EnumVariant {
                    name: "MUL86",
                    description: None,
                    value: 86,
                },
            ],
        },
        Enum {
            name: "Pllp",
            description: None,
            bit_size: 5,
            variants: &[
                EnumVariant {
                    name: "DIV2",
                    description: None,
                    value: 1,
                },
                EnumVariant {
                    name: "DIV3",
                    description: None,
                    value: 2,
                },
                EnumVariant {
                    name: "DIV4",
                    description: None,
                    value: 3,
                },
                EnumVariant {
                    name: "DIV5",
                    description: None,
                    value: 4,
                },
                EnumVariant {
                    name: "DIV6",
                    description: None,
                    value: 5,
                },
                EnumVariant {
                    name: "DIV7",
                    description: None,
                    value: 6,
                },
                EnumVariant {
                    name: "DIV8",
                    description: None,
                    value: 7,
                },
                EnumVariant {
                    name: "DIV9",
                    description: None,
                    value: 8,
                },
                EnumVariant {
                    name: "DIV10",
                    description: None,
                    value: 9,
                },
                EnumVariant {
                    name: "DIV11",
                    description: None,
                    value: 10,
                },
                EnumVariant {
                    name: "DIV12",
                    description: None,
                    value: 11,
                },
                EnumVariant {
                    name: "DIV13",
                    description: None,
                    value: 12,
                },
                EnumVariant {
                    name: "DIV14",
                    description: None,
                    value: 13,
                },
                EnumVariant {
                    name: "DIV15",
                    description: None,
                    value: 14,
                },
                EnumVariant {
                    name: "DIV16",
                    description: None,
                    value: 15,
                },
                EnumVariant {
                    name: "DIV17",
                    description: None,
                    value: 16,
                },
                EnumVariant {
                    name: "DIV18",
                    description: None,
                    value: 17,
                },
                EnumVariant {
                    name: "DIV19",
                    description: None,
                    value: 18,
                },
                EnumVariant {
                    name: "DIV20",
                    description: None,
                    value: 19,
                },
                EnumVariant {
                    name: "DIV21",
                    description: None,
                    value: 20,
                },
                EnumVariant {
                    name: "DIV22",
                    description: None,
                    value: 21,
                },
                EnumVariant {
                    name: "DIV23",
                    description: None,
                    value: 22,
                },
                EnumVariant {
                    name: "DIV24",
                    description: None,
                    value: 23,
                },
                EnumVariant {
                    name: "DIV25",
                    description: None,
                    value: 24,
                },
                EnumVariant {
                    name: "DIV26",
                    description: None,
                    value: 25,
                },
                EnumVariant {
                    name: "DIV27",
                    description: None,
                    value: 26,
                },
                EnumVariant {
                    name: "DIV28",
                    description: None,
                    value: 27,
                },
                EnumVariant {
                    name: "DIV29",
                    description: None,
                    value: 28,
                },
                EnumVariant {
                    name: "DIV30",
                    description: None,
                    value: 29,
                },
                EnumVariant {
                    name: "DIV31",
                    description: None,
                    value: 30,
                },
                EnumVariant {
                    name: "DIV32",
                    description: None,
                    value: 31,
                },
            ],
        },
        Enum {
            name: "Pllq",
            description: None,
            bit_size: 3,
            variants: &[
                EnumVariant {
                    name: "DIV2",
                    description: None,
                    value: 1,
                },
                EnumVariant {
                    name: "DIV3",
                    description: None,
                    value: 2,
                },
                EnumVariant {
                    name: "DIV4",
                    description: None,
                    value: 3,
                },
                EnumVariant {
                    name: "DIV5",
                    description: None,
                    value: 4,
                },
                EnumVariant {
                    name: "DIV6",
                    description: None,
                    value: 5,
                },
                EnumVariant {
                    name: "DIV7",
                    description: None,
                    value: 6,
                },
                EnumVariant {
                    name: "DIV8",
                    description: None,
                    value: 7,
                },
            ],
        },
        Enum {
            name: "Pllr",
            description: None,
            bit_size: 3,
            variants: &[
                EnumVariant {
                    name: "DIV2",
                    description: None,
                    value: 1,
                },
                EnumVariant {
                    name: "DIV3",
                    description: None,
                    value: 2,
                },
                EnumVariant {
                    name: "DIV4",
                    description: None,
                    value: 3,
                },
                EnumVariant {
                    name: "DIV5",
                    description: None,
                    value: 4,
                },
                EnumVariant {
                    name: "DIV6",
                    description: None,
                    value: 5,
                },
                EnumVariant {
                    name: "DIV7",
                    description: None,
                    value: 6,
                },
                EnumVariant {
                    name: "DIV8",
                    description: None,
                    value: 7,
                },
            ],
        },
        Enum {
            name: "Pllsrc",
            description: None,
            bit_size: 2,
            variants: &[
                EnumVariant {
                    name: "DISABLE",
                    description: Some("No clock selected as PLL entry clock source"),
                    value: 0,
                },
                EnumVariant {
                    name: "HSI",
                    description: Some("HSI selected as PLL entry clock source"),
                    value: 2,
                },
                EnumVariant {
                    name: "HSE",
                    description: Some("HSE selected as PLL entry clock source"),
                    value: 3,
                },
            ],
        },
        Enum {
            name: "Ppre",
            description: None,
            bit_size: 3,
            variants: &[
                EnumVariant {
                    name: "DIV1",
                    description: Some("HCLK not divided"),
                    value: 0,
                },
                EnumVariant {
                    name: "DIV2",
                    description: Some("HCLK is divided by 2"),
                    value: 4,
                },
                EnumVariant {
                    name: "DIV4",
                    description: Some("HCLK is divided by 4"),
                    value: 5,
                },
                EnumVariant {
                    name: "DIV8",
                    description: Some("HCLK is divided by 8"),
                    value: 6,
                },
                EnumVariant {
                    name: "DIV16",
                    description: Some("HCLK is divided by 16"),
                    value: 7,
                },
            ],
        },
        Enum {
            name: "Rngdiv",
            description: None,
            bit_size: 2,
            variants: &[
                EnumVariant {
                    name: "DIV1",
                    description: Some("RNG clock is not divided"),
                    value: 0,
                },
                EnumVariant {
                    name: "DIV2",
                    description: Some("RNG clock is divided by 2"),
                    value: 1,
                },
                EnumVariant {
                    name: "DIV4",
                    description: Some("RNG clock is divided by 4"),
                    value: 2,
                },
                EnumVariant {
                    name: "DIV8",
                    description: Some("RNG clock is divided by 8"),
                    value: 3,
                },
            ],
        },
        Enum {
            name: "Rngsel",
            description: None,
            bit_size: 2,
            variants: &[
                EnumVariant {
                    name: "DISABLE",
                    description: Some("No clock used as RNG clock source"),
                    value: 0,
                },
                EnumVariant {
                    name: "HSI_DIV_8",
                    description: Some("HSI divided by 8 used as RNG clock source"),
                    value: 1,
                },
                EnumVariant {
                    name: "SYS",
                    description: Some("SYSCLK used as RNG clock source"),
                    value: 2,
                },
                EnumVariant {
                    name: "PLL1_Q",
                    description: Some("PLLQCLK used as RNG clock source"),
                    value: 3,
                },
            ],
        },
        Enum {
            name: "Rtcsel",
            description: None,
            bit_size: 2,
            variants: &[
                EnumVariant {
                    name: "DISABLE",
                    description: Some("No clock used as RTC clock"),
                    value: 0,
                },
                EnumVariant {
                    name: "LSE",
                    description: Some("LSE used as RTC clock"),
                    value: 1,
                },
                EnumVariant {
                    name: "LSI",
                    description: Some("LSI used as RTC clock"),
                    value: 2,
                },
                EnumVariant {
                    name: "HSE_DIV_32",
                    description: Some("HSE divided by 32 used as RTC clock"),
                    value: 3,
                },
            ],
        },
        Enum {
            name: "Sw",
            description: None,
            bit_size: 3,
            variants: &[
                EnumVariant {
                    name: "HSI",
                    description: Some("HSI selected as system clock"),
                    value: 0,
                },
                EnumVariant {
                    name: "HSE",
                    description: Some("HSE selected as system clock"),
                    value: 1,
                },
                EnumVariant {
                    name: "PLL1_R",
                    description: Some("PLLRCLK selected as system clock"),
                    value: 2,
                },
                EnumVariant {
                    name: "LSI",
                    description: Some("LSI selected as system clock"),
                    value: 3,
                },
                EnumVariant {
                    name: "LSE",
                    description: Some("LSE selected as system clock"),
                    value: 4,
                },
            ],
        },
        Enum {
            name: "Tim15sel",
            description: None,
            bit_size: 1,
            variants: &[
                EnumVariant {
                    name: "PCLK1_TIM",
                    description: Some("TIMPCLK used as TIM15 clock source"),
                    value: 0,
                },
                EnumVariant {
                    name: "PLL1_Q",
                    description: Some("PLLQCLK used as TIM15 clock source"),
                    value: 1,
                },
            ],
        },
        Enum {
            name: "Tim1sel",
            description: None,
            bit_size: 1,
            variants: &[
                EnumVariant {
                    name: "PCLK1_TIM",
                    description: Some("TIMPCLK used as TIM1 clock source"),
                    value: 0,
                },
                EnumVariant {
                    name: "PLL1_Q",
                    description: Some("PLLQCLK used as TIM1 clock source"),
                    value: 1,
                },
            ],
        },
        Enum {
            name: "Usartsel",
            description: None,
            bit_size: 2,
            variants: &[
                EnumVariant {
                    name: "PCLK1",
                    description: Some("PCLK used as USART clock source"),
                    value: 0,
                },
                EnumVariant {
                    name: "SYS",
                    description: Some("SYSCLK used as USART clock source"),
                    value: 1,
                },
                EnumVariant {
                    name: "HSI",
                    description: Some("HSI used as USART clock source"),
                    value: 2,
                },
                EnumVariant {
                    name: "LSE",
                    description: Some("LSE used as USART clock source"),
                    value: 3,
                },
            ],
        },
        Enum {
            name: "Usbsel",
            description: None,
            bit_size: 2,
            variants: &[
                EnumVariant {
                    name: "HSI48",
                    description: Some("HSI48 used as USB clock source"),
                    value: 0,
                },
                EnumVariant {
                    name: "HSE",
                    description: Some("HSE used as USB clock source"),
                    value: 1,
                },
                EnumVariant {
                    name: "PLL1_Q",
                    description: Some("PLLQCLK used as USB clock source"),
                    value: 2,
                },
            ],
        },
    ],
};
